96 lines
4.0 KiB
Markdown
96 lines
4.0 KiB
Markdown
# How AVX2 works
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🌐 **English** · [Dansk](How-AVX2-Works-da) · [Bahasa Melayu](How-AVX2-Works-ms)
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AVX2 is a set of CPU instructions that do the same operation on several
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numbers at once (SIMD: single instruction, multiple data). `is_prime_avx2`
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uses it to test **four divisors per step** instead of one.
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## The idea
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A number `n` is prime if no number from 2 to sqrt(n) divides it. Two steps
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shrink the work:
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1. **Skip most candidates.** Every prime above 3 has the form 6k - 1 or 6k + 1
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(5, 7, 11, 13, 17, 19, 23, 25, ...). Even numbers and multiples of 3 are
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rejected before the loop, so only these divisors are tried.
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2. **Test four at a time.** One 256-bit AVX2 register holds four `double`
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values, so one divide, one multiply and one compare handle four divisors.
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Each loop pass tests the divisors `d, d+2, d+6, d+8` and then moves 12 forward:
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`5,7,11,13` then `17,19,23,25` then `29,31,35,37`, and so on.
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## The code, step by step
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```c
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// Only divisors up to sqrt(n) need testing: a factor above it pairs with one below it.
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const double limit = floor(sqrt((double)n));
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// Broadcast n and the limit into all 4 double lanes of a 256-bit register.
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__m256d v_n = _mm256_set1_pd((double)n);
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__m256d v_limit = _mm256_set1_pd(limit);
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// Divisors 5, 7, 11, 13 (6k +/- 1); each iteration advances by 12.
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// Kept as 4 x int32 in a 128-bit register, converted to double each pass.
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__m128i v_div_i = _mm_setr_epi32(5, 7, 11, 13);
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const __m128i v_step = _mm_set1_epi32(12);
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// base is the first divisor of the group; stop when it passes sqrt(n).
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for (double base = 5.0; base <= limit; base += 12.0) {
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// Convert the 4 int32 divisors to 4 doubles.
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__m256d v_d = _mm256_cvtepi32_pd(v_div_i);
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// q = floor(n / d) for all 4 divisors at once.
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__m256d v_q = _mm256_floor_pd(_mm256_div_pd(v_n, v_d));
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// rem = n - q * d, which is n mod d.
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__m256d v_rem = _mm256_sub_pd(v_n, _mm256_mul_pd(v_q, v_d));
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// Lane mask: all bits set where the remainder is 0 (d divides n).
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__m256d is_zero = _mm256_cmp_pd(v_rem, _mm256_setzero_pd(), _CMP_EQ_OQ);
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// Lane mask: all bits set where the divisor is <= sqrt(n).
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__m256d in_range = _mm256_cmp_pd(v_d, v_limit, _CMP_LE_OQ);
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// A lane only counts if it divides n and the divisor is <= sqrt(n).
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// movemask packs the sign bit of each lane into 4 bits; non-zero = a hit.
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if (_mm256_movemask_pd(_mm256_and_pd(is_zero, in_range)) != 0)
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return false;
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// Move to the next four divisors: 5,7,11,13 -> 17,19,23,25 -> ...
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v_div_i = _mm_add_epi32(v_div_i, v_step);
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}
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// No divisor found up to sqrt(n): n is prime.
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```
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## Why the `in_range` mask is needed
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The last group can contain divisors above sqrt(n). Without the mask such a
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lane could report a "factor" that is not one. For `n = 25` the limit is 5, so
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only lane 0 (divisor 5) counts and 25 is correctly rejected; for `n = 29`
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nothing divides it and 29 is prime.
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## Why `double` and not `float` or integers
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AVX2 has no integer divide, so the division is done in floating point. A
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`double` holds every 32-bit integer exactly and IEEE division is correctly
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rounded, so `floor(n / d)` is exact for `n` up to `UINT32_MAX`. A 32-bit
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`float` has only 24 bits of precision and would give wrong quotients. This is
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also why the function supports `n` only up to 4,294,967,295.
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## Intrinsics used
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| Intrinsic | What it does |
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| --- | --- |
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| `_mm256_set1_pd` | copy one double into all 4 lanes |
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| `_mm_setr_epi32` | build 4 int32 values in order |
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| `_mm256_cvtepi32_pd` | convert 4 int32 to 4 double |
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| `_mm256_div_pd` / `_mm256_mul_pd` / `_mm256_sub_pd` | divide, multiply, subtract in 4 lanes |
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| `_mm256_floor_pd` | round 4 doubles down |
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| `_mm256_cmp_pd` | compare 4 lanes, giving an all-ones or all-zeros mask per lane |
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| `_mm256_and_pd` | bitwise AND of two masks |
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| `_mm256_movemask_pd` | collapse the 4 lane masks into a 4-bit integer |
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| `_mm_add_epi32` | add 4 int32 values |
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They come from `<immintrin.h>`. Build with `-mavx2` (gcc/clang) or
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`/arch:AVX2` (MSVC); on a CPU without AVX2 the program would crash with an
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illegal instruction.
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